1G Ethernet MAC IP core 검색…
구글링하다가 계속 일회성이라 검색된 결과 중 들어가 본 곳만 저장할 겸 해서
아래 내용 중 가장 인상적인 것은 750불 짜리 소스를 판매하는 곳이 있다는 것. 보통 오픈 안하고 막상 알아보면 엄청 비싼데. 싼게 비지떡이겠죠 ^^
pkerling/ethernet_mac
https://github.com/pkerling/ethernet_mac
Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
This page is a short overview of the features and usage of the MAC. More information on the design and implementation can be found in the design document at https://github.com/pkerling/ethernet_mac_doc/raw/master/Thesis.pdf.
테스트 보드는 아래 보드.
https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE0600-Spartan-6-Ethernet/
Opencores 10_100_1000 Mbps tri-mode ethernet MAC
https://opencores.org/project/ethernet_tri_mode
GRETH_GBIT 10/100/1000 Ethernet MAC
https://www.gaisler.com/j25/index.php/products?option=com_content&task=view&id=278
The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple ethernet packets can be received and transmitted without CPU involvement. The GRETH_GBIT provides support for the MII and GMII PHY interfaces. Hardware support is also provided for the EDCL UDP debugging protocol. For critical space applications, a fault-tolerant version of GRETH_GBIT is available with full SEU protection of all RAM blocks.
Deliverables • VHDL source code or FPGA/ASIC netlist
Triple-Speed Ethernet Intel® FPGA IP Core
The Triple-Speed Ethernet Intel® FPGA IP core consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sublayer (PCS) intellectual property (IP). This IP function enables Intel FPGAs to interface to an external Ethernet PHY device, which interfaces to the Ethernet network.
This IP is offered in MAC-only mode or in MAC+PHY mode. In the MAC only mode, the IP uses an external PHY chip to do signaling. The two supported interfaces to the external PHYs are: GMII (8 bit interface at 125 MHz SDR) and RGMII (4 bit interface at 125 MHz DDR). In the MAC+PHY mode, the PHY is realized using on-chip transceivers or LVDS I/O with dynamic phase alignment (DPA) logic that can operate up to 1.25 Gbps. SGMII or 1000Base-X protocol is used in this case. The usage of LVDS I/Os enables very scalable multiport gigabit Ethernet (GbE) system designs while saving the serial transceivers for higher performance protocols.
emsys Gigabit Ethernet IP Core
https://www.emsys.de/products/gbit-ethernet-ip
emsys Embedded Systems GmbH has long time experience with development of reusable hardware IP.
The emsys Gigabit Ethernet core is a scalable, high performance IP module for usage in ASIC and FPGA designs to integrate an IEEE 802.3 Gigabit Ethernet Controller into embedded systems. It provides an easy to use programming interface for interconnecting almost any 8/16/32 bit microcontroller or DSP and is optimized for camera/visual applications.
Deliverables
The emsys Gigabit Ethernet IP core can be ordered as:
VHDL Source code for ASIC designs
Synopsys Design Ware component for ASIC designs
VHDL/Verilog netlist for FPGA designs (Xilinx, Actel, Altera)
MorethanIP 10/100/1000 Ethernet MAC
http://www.morethanip.com/mbps_10_100_1000_mac.htm
COM-5401SOFTTri-Mode 10/100/1000 Ethernet MAC
VHDL source code for Tri-Mode 10/100/1000 Mbps Ethernet MAC |
| $750 |
https://comblock.com/download/com5401soft.pdf
The COM-5401SOFT is a generic tri-mode Ethernet MAC core (including the VHDL source code) designed to support full- or half-duplex Gigabit throughput on low-cost FPGAs. The component's very efficient implementation makes it suitable for multiple instantiations within a small FPGA. For example, it is instantiated four times (for a 4 Gbits/s combined throughput) in a small Spartan-6 XC6SLX16 [4][5].
Xilinx Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC
https://www.xilinx.com/support/documentation/user_guides/ug074.pdf
CAST EMAC-1G
http://www.cast-inc.com/ip-cores/interfaces/emac-1g/index.html
Arasan Gigabit Ethernet with IEEE 1588 and AVB
https://www.arasan.com/products/ethernet/1ge-1588/
DELIVERABLES
- RMM Compliant Synthesizable RTL design in Verilog
Lattice Tri-Speed Ethernet MAC Core IP
The Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbits/sec data rate) or the Fast Ethernet mode (10/100 Mbits/sec data rate). Operation in either Gigabit mode or Fast Ethernet mode is selected by setting an internal register bit.